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| 型號： | TLC320AD58CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 186K |
| 代理商： | TLC320AD58CDW |
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2–1
2 Detailed Description
The sigma-delta converter allows for simple antialias external filtering. Typically, a first order RC filter is
sufficient.
2.1
Power-Down and Reset Functions
2.1.1
Power Down
The power-down state is comprised of a separate digital and analog power down. The power consumption
of each is detailed in the electrical characteristics section.
The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set
to an unasserted level. When the digital power-down terminal is pulled high, normal operation of the device
is initiated. In slave mode, the conversion process must synchronize to an input on the LRClk terminal as
well as the SCLK terminal. Therefore, the conversion process is not initiated until the first rising edges of
both SCLK and LRClk are detected after DigPD is pulled high. This synchronizes the conversion cycle; all
conversions are performed at a fixed LRClk rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)]
after the initial synchronization. After the digital power-down terminal is brought high, the output of the digital
filters remains invalid for 50 LRClk cycles [see Figures 2–1(a) and 2–1(b)].
In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing.
The first valid data out occurs as shown in Figure 2–1(c).
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid which renders the outputs of the digital filters invalid. When the analog power-down terminal is
brought high, the modulators are brought back online; however, the outputs of the digital filters require 50
LRClk cycles for valid results.
2.1.2
Reset Function
The conversion process is not initiated until the first rising edges of both SCLK and LRClk are detected after
DigPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRClk
rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)] after the initial synchronization.
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