參數(shù)資料
型號(hào)： TLC320AD58CDW
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： PLASTIC, SO-28
文件頁(yè)數(shù)： 25/27頁(yè)
文件大?。?/td> 186K
代理商： TLC320AD58CDW
1–3
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
INLM
2
I
Inverting input to left analog input amplifier
INLP
1
I
Noninverting input to left analog input amplifier
INRM
27
I
Inverting input to right analog input amplifier
INRP
28
I
Noninverting input to right analog input amplifier
LGND
25
I
Logic power supply ground for analog modulator
LRClk
14
I/O
Left/right clock. LRClk signifies whether the serial data is associated with the left channel
ADC (when LRClk is high) or the right channel ADC (when LRClk is low). LRClk is low
when DigPD is low.
MCLK
20
I
Master clock. MCLK is used to derive all the key logic signals of the sigma-delta audio
ADC. The nominal input frequency range is 18.432 MHz to 256 kHz.
MODE(0–2)
13, 22,
8
I
Serial modes. MODE(0–2) configure this device for many different modes of operation.
The different configurations are:
Master versus slave
16 bit versus 18 bit
MSB first versus LSB first
Slave: Fsync controlled versus Fsync high
Each of these modes is described in the serial interface section along with timing
diagrams.
MODE
MASTER/
MSB/LSB
0 1 2
SLAVE
BITS
FIRST
0 0 0
slave
up to 18
MSB
0 0 1
slave
18
LSB
0 1 0
slave
up to 18
MSB
0 1 1
master
16
MSB
1 0 0
master
18
MSB
1 0 1
master
18
LSB
1 1 0
master
16
MSB
1 1 1
master
16
LSB
OSFL,
OSFR
9, 21
O
Over scale flag left/right. If the left/right channel digital output exceeds full scale output
range for two consecutive conversions, this flag is set high for 4096 LRClk periods.
OSFL and OSFR are low when DigPD is low.
SCLK
15
I/O
Shift clock. If SCLK is configured as an input, SCLK is used to clock serial data out of
the sigma-delta audio ADC. If SCLK is configured as an output, SCLK stops clocking
when DigPD is low.
TEST1
7
I
Test mode 1. TEST1 should be low for normal operation.
TEST2
11
I
Test mode 2. TEST2 should be low for normal operation.
REFI
3
I
Input voltage for modulator reference (normally connected to REFO, terminal 26).
REFO
26
I
Internal voltage reference
Vlogic
24
I
Logic power supply voltage (5 V) for analog modulator
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD58CDWR 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD75 制造商:TI 制造商全稱:Texas Instruments 功能描述:20-Bit Sigma-Delta Stereo ADA Circuit
TLC320AD75C 制造商:TI 制造商全稱:Texas Instruments 功能描述:20-Bit Sigma-Delta Stereo ADA Circuit
TLC320AD75CDL 制造商:Texas Instruments 功能描述:
TLC320AD77 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec
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