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參數(shù)資料
| 型號(hào)： | TLC320AD58CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 186K |
| 代理商： | TLC320AD58CDW |
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1–2
1.3
Terminal Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INLP
INLM
REFI
AVDD
AVSS
AnaPD
TEST1
MODE2
OSFL
DigPD
TEST2
CMODE
MODE0
LRClk
INRP
INRM
REFO
LGND
Vlogic
NC
MODE1
OSFR
MCLK
DVSS
DVDD
Fsync
DOUT
SCLK
DW PACKAGE
(TOP VIEW)
NC – No internal connection
1.4
Ordering Information
PACKAGE
TA
SMALL OUTLINE
(DW)
0
°C to 70°C
TLC320AD58CDW
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AnaPD
6
I
Analog power-down mode. The analog power-down mode disables the analog
modulators. The single-bit modulator outputs become invalid, rendering the outputs of the
digital filters invalid. When AnaPD is pulled high, normal operation of the device is
resumed.
AVDD
4
I
Analog supply voltage
AVSS
5
I
Analog ground
CMODE
12
I
Clock mode. CMODE is used to select between two methods of determining the master
clock frequency. When CMODE is high, the master clock input is 384
× the conversion
frequency. When CMODE is low, the master clock input is 256
× the conversion frequency.
DOUT
16
O
Data output. DOUT is used to transmit the sigma-delta audio ADC output data to a DSP
serial port or other compatible serial interface and is synchronized to SCLK. This output
is low when DigPD is high.
DVDD
18
I
Digital supply voltage
DVSS
19
I
Digital ground
DigPD
10
I
Digital power-down mode. The digital power-down mode shuts down the digital filters and
clock generators. All digital outputs are brought to unasserted states. When DigPD is
pulled high, normal operation of the device is resumed.
Fsync
17
I/O
Frame sync. Frame sync is used to designate the valid data from the ADC.
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