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參數(shù)資料
| 型號(hào)： | TLC320AD57CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 129K |
| 代理商： | TLC320AD57CDW |
3–3
3.3.2.2
Inputs/Supplies, TA = 25°C, AVDD = DVDD = 5 V, fs = 48 kHz, Bandwidth = 24 kHz,
HPByp = 1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Input voltage
Differential input
6.4
V
Input voltage
Single-ended input
3.2
V
Input impedance
50
k
POWER SUPPLIES
IDD (analog), operating
22
30
mA
Power supply current
IDD (digital), operating
24
32
mA
Power-supply current
IDD (analog), power down
100
A
IDD (digital), power down
40
A
Power dissipation
230
mW
3.3.3
Channel Characteristics, TA = 25°C, AVDD=DVDD = 5 V, fs = 48 kHz, HPByp = 1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Passband (– 3 dB)
HPByp = 0
0.001
24
kHz
Passband ripple
30 Hz – 21.8 kHz
±0.01
dB
Stopband attenuation
26.2 kHz – 3046 kHz
80
dB
Group delay
25/Fs
s
3.4
Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
td1
Delay time, AnaPD
↓ to DOUT valid (see Figure 2–1(c))
30
ns
td(MFSD)
Delay time, SCLK
↓ to Fsync, master mode
(see Figures 4–1, 4–2, 4–3, and 4–4)
– 20
20
ns
td(MDD)
Delay time, SCLK
↓ to DOUT, master mode
(see Figures 4–1, 4–2, 4–3, and 4–4)
0
50
ns
td(MIRD)
Delay time, SCLK
↓ to LRClk, master mode
(see Figures 4–2 and 4–4)
– 20
20
ns
td(SDD1)
Delay time, LRClk to DOUT, slave mode (see Figure 4–5)
50
ns
td(SDD2)
Delay time, SCLK
↓ to DOUT, slave mode
(see Figures 4–5 and 4–6)
50
ns
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