參數(shù)資料
型號(hào)： TLC320AD57CDW
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： PLASTIC, SO-28
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 129K
代理商： TLC320AD57CDW
3–1
3 Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Analog supply voltage range, AVDD (see Note 1)
– 0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . .
Digital supply voltage range, DVDD (see Note 2)
– 0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . .
Digital output voltage range, (externally applied)
– 0.3 V to DVDD ) 0.3 V
. . . . . . . . . . .
Digital input voltage range, MODE0 – MODE2
– 0.3 V to DVDD ) 0.3 V
. . . . . . . . . . . .
Analog input voltage range, INLP, INLM, INRP, INRM
– 0.3 V to AVDD ) 0.3 V
. . . . . .
Operating free-air temperature range, TA
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
– 65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds, TC
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
. . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTES:
1. Voltage values for maximum ratings are with respect to AVSS.
2. Voltage values for maximum ratings are with respect to DVSS.
3.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Analog supply voltage, AVDD (see Note 3)
4.75
5
5.25
V
Digital supply voltage, DVDD
4.75
5
5.25
V
Analog logic supply voltage, at Vlogic
4.75
5
5.25
V
Reference voltage, Vref
3.2
V
Setup time, DigPD
↓ to LRClk↑, slave mode, tsu1 (see Figure 2–1(a))
30
ns
Setup time, DigPD
↓ to LRClk↑, master mode, tsu2 (see Figure 2–1(b))
30
ns
Setup time, SCLK
↑ to LRClk, slave mode, tsu3 (see Figures 4–5 and 4–6)
30
ns
Setup time, LRClk to SCLK
↑, slave mode, tsu4 (see Figure 4–5)
30
ns
Setup time, SCLK
↑ to Fsync, slave mode, tsu5 (see Figure 4–6)
30
ns
Setup time, Fsync to SCLK
↑, slave mode, tsu6 (see Figure 4–6)
30
ns
Load resistance at DOUT, RL
10
k
Operating free-air temperature, TA
0
70
°C
NOTE 3: Voltages at analog inputs and outputs and AVDD are with respect to the AVSS terminal.
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