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參數(shù)資料
| 型號(hào)： | TLC320AD57CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 129K |
| 代理商： | TLC320AD57CDW |
2–3
2.2
Differential Input
The input is differential in order to provide common-mode noise rejection and increase the input dynamic
range. Figure 2–2 shows the analog input signals used in a differential configuration to achieve
6.4-V peak-to-peak differential swing with a 3.2-V peak-to-peak swing per input line.
TLC320AD57
INLP, INRP
INLM, INRM
4.1 V
2.5 V
0.9 V
4.1 V
2.5 V
0.9 V
Figure 2–2. Differential Analog Input Configuration
2.3
Sigma-Delta Modulator
The modulator is a fourth order sigma-delta modulator with 64 times oversampling. The ADC provides
high-resolution, low-noise performance from a one-bit converter using oversampling techniques.
2.4
Decimation Filter
The decimation filter used after the sigma-delta modulator reduces the digital data rate to the sampling rate
of LRClk. This is accomplished by decimating with a ratio of 1:64. The output of this filter is a 2s complement
data word of up to 18 bits serially clocked out.
If the input value exceeds the full range of the converter, the output of the decimator is held at the appropriate
extreme until the input returns to within the dynamic range of the device.
2.5
High-Pass Filter
The high-pass filter removes dc from the input. With this filtering, offset calibration is not needed. The
high-pass filter can be circumvented by asserting the HPByp terminal to pass dc signals through the
converter. However, an offset due to the converter can be present when bypassing the high-pass filter.
2.6
Master-Clock Circuit
The master-clock circuit generates and distributes necessary clocks throughout the device. MCLK is the
external master-clock input. CMODE selects the relationship of MCLK to the sample rate, LRClk. When
CMODE is low, the sample rate of the data paths is set to LRClk = MCLK /256. When CMODE is high, the
sample rate is set to LRClk = MCLK /384. With a fixed oversampling ratio of 64
×, the effect of changing MCLK
is shown in Table 2–1.
When the device is in master mode, SCLK is derived from MCLK in order to provide clocking of the serial
communications between the sigma-delta audio ADC and a digital signal processor (DSP) or control logic.
This is equivalent to a clock running at 64
× LRClk.
When the device is in slave mode, SCLK is externally derived.
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| TLC320AD57CDWR | 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
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| TLC320AD57CDWR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
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| TLC320AD58CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58CDWR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
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