參數(shù)資料
型號: tlc320ad56c
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
中文描述: sigma - delta模擬接口電路(Σ-Δ模擬接口電路)
文件頁數(shù): 28/38頁
文件大?。?/td> 253K
代理商: TLC320AD56C
4–5
4.3.7
DAC Dynamic Performance, DV
DD
= 5 V or 3 V
DAC Signal-to-Noise (see Note 7)
PARAMETER
4.3.7.1
TEST CONDITIONS
VO = 0 dB
VO = –9 dB
VO = –40 dB
VO = –65 dB
MIN
80
TYP
85
MAX
UNIT
Signal
i
i (SNR)
dB
72
77
41
16
46
21
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.
4.3.7.2
DAC Signal-to-Distortion (see Note 7)
PARAMETER
TEST CONDITIONS
VO = 0 dB
VO = –9 dB
VO = –40 dB
VO = –65 dB
MIN
86
TYP
92
MAX
UNIT
Signal-to-total harmonic distortion (THD)
i di
dB
90
96
60
40
66
46
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.
4.3.7.3
DAC Signal-to-Distortion+Noise (see Note 7)
PARAMETER
TEST CONDITIONS
VO = 0 dB
VO = –9 dB
VO = –40 dB
VO = –65 dB
MIN
80
TYP
84
MAX
UNIT
Total harmonic distortion + noise (THD+N)
i di
(THD N)
dB
72
76
41
16
45
20
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.
相關(guān)PDF資料
PDF描述
TLC320AD57(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
TLC320AD57C Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD58(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
TLC320AD58C Sigma-Delta Stereo Analog-to-Digital Converter
TLC320AD75C 20-Bit Sigma-Delta Stereo ADA Circuit
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