參數(shù)資料
型號(hào)： TLC320AD55CDW
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： PLASTIC, SOP-28
文件頁(yè)數(shù)： 17/41頁(yè)
文件大?。?/td> 203K
代理商： TLC320AD55CDW
3–6
Example 2: All variables above remain the same except Fsclk = 1, SCLK = 2.048 MHz = sample
rate
× 256. In this configuration, two consecutive primary communications represent the
same data sample.
3.4
FIR Bypass Mode
An option is provided to bypass the FIR sections of the decimation filter and the interpolation filter. This is
selected through the control 2 register. The sinc filters of the two paths cannot be bypassed.
The timing requirements for this mode of operation are shown in Figure 3 –7.
ADC Data
Out
DOUT
Primary
Secondary
Primary
Secondary
Primary
18 – 4
DIN
3–0
See Note A
16 FCLKS
FS
ADC Data
Out
ADC Data
Out
NOTE A: The number of clocks between primary cycles is a function of FCLK. When either FIR is bypassed, this period
is 16 FCLKs. See Fk divide register in Appendix A.
Figure 3– 7. FIR Bypass Timing
相關(guān)PDF資料
PDF描述
TLC320AD55CDWR SPECIALTY ANALOG CIRCUIT, PDSO28
TLC320AD57CDW 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
TLC320AD57CDWR 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
TLC320AD58CDWR 2-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
TLC320AD58CDW 2-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
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