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參數(shù)資料
| 型號(hào)： | TLC320AD55CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOP-28 |
| 文件頁(yè)數(shù)： | 15/41頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | TLC320AD55CDW |
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3–4
Table 3–1. Least-Significant-Bit Control Function
CONTROL BIT D0
CONTROL BIT FUNCTION
0
No operation (no-op)
1
Secondary communication request
On the falling edge of the next FS, D15 through D1 is input to DIN or D15 through D0 is output to DOUT.
When a secondary communication request is made, FS goes low for 32 FCLKs (see Fk divide register,
Appendix A) after the beginning of the primary frame.
Communication Frame 2 (CF2)
DOUT
DIN
DAC Data In
ADC Data
Out
DAC Data In
All Bits 0
Secondary
Update
16 SCLKs
64 FCLKs
16
SCLKs
16 SCLKs
FS
FC
(Secondary
Read)
(Secondary
Read or Write)
Communication Frame 1 (CF1)
No Secondary
Request
ADC Data
Out
ADC Data
Out
ADC Data
Out
(Secondary
Write)
Primary
Secondary
Primary
64 FCLKs
Register
Data
32 FCLKs
(128 SCLKs when Fk = Fsclk)
See Fk divide register in Appendix A.
For a selected MCLK, Fk and Fsclk: SCLK = 2 Fk/Fsclk
× FCLK
8
SCLKs
Figure 3– 5. Hardware FC Secondary Request
(Phone Mode Disabled)
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