參數(shù)資料
型號(hào): TLC320AD50IPT
廠(chǎng)商: Texas Instruments, Inc.
英文描述: SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
中文描述: sigma - delta模擬接口,具有大師電路,從功能
文件頁(yè)數(shù): 45/84頁(yè)
文件大?。?/td> 447K
代理商: TLC320AD50IPT
3–6
3.5.10
Power-Supply Rejection, V
DD
= 5 V (Unless Otherwise Noted) (see Note 17)
PARAMETER
TEST CONDITIONS
fi = 0 to 30 kHz
fi = 30 to 50 kHz
fi = 0 to 30 kHz
fi = 30 to 50 kHz
fi = 0 to 30 kHz
fi = 30 to 50 kHz
Single ended,
fi = 0 to 30 kHz
fi = 30 to 50 kHz
Differential,
fi = 0 to 30 kHz
fi = 30 to 50 kHz
MIN
TYP
MAX
UNIT
ADC VDD
Supply voltage rejection ratio ADC channel
Supply-voltage rejection ratio, ADC channel
50
55
DAC VDD
Supply voltage rejection ratio DAC channel
Supply-voltage rejection ratio, DAC channel
40
45
DGTL VDD
Supply voltage rejection ratio ADC channel
Supply-voltage rejection ratio, ADC channel
50
55
dB
40
DGTL VDD
Supply voltage rejection ratio DAC channel
Supply-voltage rejection ratio, DAC channel
45
40
45
All typical values are at VDD = 5 V and TA = 25
°
C.
NOTE 17: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.
3.5.11
Crosstalk Attenuation, V
DD
= 5 V (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC channel crosstalk attenuation
DAC channel idle with
DIN = 00000000000000,
ADC input = 0 dB,
1020-Hz sine wave,
Gain = 0 dB (see Note 18)
80
dB
DAC channel crosstalk attenuation
ADC channel idle with INP, INM,
AUX IN+, and AUX IN– at ADC VMID
DAC channel input = digital equivalent
of a 1020-Hz sine wave (see Note 19)
80
dB
80
All typical values are at VDD = 5 V and TA = 25
°
C.
NOTES: 18. The test signal is a 1020-Hz sine wave with a 0 dB = 6-V peak-to-peak reference level for the analog input
signal.
19. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600
from OUT+ to OUT–.
相關(guān)PDF資料
PDF描述
TLC320AD50(中文) Sigma-Delta Analog Interface Circuit With Master-Slave Function(Sigma-Delta 模擬接口具主從功能)
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