- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383954 > TLC320AD50IPT (Texas Instruments, Inc.) SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION PDF資料下載
參數(shù)資料
| 型號： | TLC320AD50IPT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| 中文描述： | sigma - delta模擬接口，具有大師電路，從功能 |
| 文件頁數(shù)： | 26/84頁 |
| 文件大?。?/td> | 447K |
| 代理商： | TLC320AD50IPT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
2–11
2.13.1
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through
3 of the B cycle description in the master mode but differs as follows:
Slave and Codec Functional Sequence
1.
Same as master
2.
Same as master
3.
Same as master
4.
All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle.
5.
All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes
low. This operation provides the synchronization necessary when using an external FS signal.
6.
The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.
In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC if the free-run function has not been
selected (see Subsection 2.15.4). In the codec mode, there is usually no need for phase adjustments;
however, any required phase adjustments must be made by adjusting the external frame-sync timing
(sampling time).
2.13.2
When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary frame-
sync interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that
frame- sync interval. After the FSD register programming is completed for the master and slave, the slave
primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host
serial port for data transfers for itself and all slave devices.
Slave Register Programming
The number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync
intervals generated by the master is equal to the number of slaves plus one (see Section 2.7). These master
frame-sync intervals are separated in time by the delay time specified by the FSD register (register 7). These
master-generated intervals are the only frame-sync interval signals applied to the host serial port to provide
the data-transfer time slot for the slave devices.
2.14 Terminal Functions
2.14.1
Frame-Sync Function
The frame-sync signal indicates that the device is ready to send and receive data for both master and slave
modes. The data transfer begins on the falling edge of the frame-sync signal.
2.14.1.1 Frame Sync (FS), Master Mode
The frame sync is generated internally. FS goes low on the rising edge of SCLK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
sync for each slave that is being used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC320AD50(中文) | Sigma-Delta Analog Interface Circuit With Master-Slave Function(Sigma-Delta 模擬接口具主從功能) |
| TLC34075A-110 | Color-Palette(110MHz,視頻接口調(diào)色器) |
| TLC34075A-135 | Color-Palette(135MHz,視頻接口調(diào)色器) |
| TLC34075A-66 | Color-Palette(66MHz,視頻接口調(diào)色器) |
| TLC34075A-85 | Color-Palette(85MHz,視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD52CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C-I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。