參數(shù)資料
型號： TLC2932PW
廠商： Texas Instruments, Inc.
英文描述： HIGH-PERFORMANCE PHASE-LOCKED LOOP
中文描述： 高性能鎖相環(huán)
文件頁數(shù)： 7/24頁
文件大?。?/td> 418K
代理商： TLC2932PW
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, V
DD
= 5 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
VIT
II
Zi(VCO IN)
IDD(INH)
IDD(VCO)
NOTES:
High-level output voltage
IOH = –2 mA
IOL = 2 mA
4
V
Low-level output voltage
0.5
V
Input threshold voltage at SELECT, VCO INHIBIT
1.5
2.5
3.5
±
1
V
μ
A
M
μ
A
mA
Input current at SELECT, VCO INHIBIT
VI = VDD or GND
VCO IN = 1/2 VDD
See Note 4
Input impedance
10
VCO supply current (inhibit)
0.01
1
VCO supply current
See Note 5
15
35
4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 k
, VCO INHIBIT = GND, and PFD is inhibited.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High-level output voltage
IOH = 2 mA
IOL = 2 mA
PFD INHIBIT = high,
VI = VDD or GND
4.5
V
Low-level output voltage
0.2
V
IOZ
High-impedance-state output current
±
1
μ
A
VIH
VIL
VIT
Ci
Zi
IDD(Z)
IDD(PFD)
NOTES:
High-level input voltage at FIN–A, FIN–B
4.5
V
Low-level input voltage at FIN–A, FIN–B
1
V
Input threshold voltage at PFD INHIBIT
1.5
2.5
3.5
V
Input capacitance at FIN–A, FIN–B
5
pF
M
μ
A
mA
Input impedance at FIN–A, FIN–B
10
High-impedance-state PFD supply current
See Note 6
0.01
1
PFD supply current
See Note 7
0.15
3
6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, no load, and
VCO OUT is inhibited.
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