參數(shù)資料
型號(hào)： TLC2932PW
廠(chǎng)商： Texas Instruments, Inc.
英文描述： HIGH-PERFORMANCE PHASE-LOCKED LOOP
中文描述： 高性能鎖相環(huán)
文件頁(yè)數(shù)： 15/24頁(yè)
文件大小： 418K
代理商： TLC2932PW
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
countdown N value depends on the input
frequency and the desired VCO output frequency
according to the system application requirements.
The K
p
and K
V
values are obtained from the
operating characteristics of the device as shown
in Figure 24. K
p
is defined from the phase detector
V
OL
and V
OH
specifications and the equation
shown in Figure 24(b). K
V
is defined from
Figures 8, 9, 10, and 11 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
K
V
: VCO gain (rad/s/V)
K
p
: PFD gain (V/rad)
K
f
: LPF gain (V/V)
K
N
: count down divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V
DD
applied to the VCO IN terminal. However,
for optimum temperature performance, a resistor value of 3.3 k
with a 3-V supply and a resistor value of 2.5
k
for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice
but a carbon-compositiion resistor can be used with excellent results also. A 0.22
μ
F capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
H
0.8 Kp
KV
Kf(
)
Where
K
f
(
∞
) = the filter transfer function value at
ω
=
∞
Divider
(KN = 1/N)
PFD
(Kp)
VCO
(KV)
LPF
(Kf)
TLC2932
f REF
VOH
fMAX
fMIN
VIN MIN
VIN MAX
–2
π
2
π
–
π
0
π
Range of
Comparison
VOH
VOL
Kp =
VOH – VOL
4
π
KV =
2
π
(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 24. Example of a PLL Block Diagram
(a)
(b)
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