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參數(shù)資料
| 型號(hào)： | TLC2932PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| 中文描述： | 高性能鎖相環(huán) |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 418K |
| 代理商： | TLC2932PW |
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VCO output frequency 1/2 divider
The TLC2932 SELECT terminal sets the f
osc
or 1/2 f
osc
VCO output frequency as shown in Table 1. The 1/2
f
osc
output should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELECT
VCO OUTPUT
Low
fosc
1/2 fosc
High
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
VCO OSCILLATOR
VCO OUTPUT
IDD(VCO)
Normal
Low
Active
Active
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN–A
FIN–B
PFD OUT
VOH
Hi-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT
DETECTION
PFD OUTPUT
IDD(PFD)
Normal
Low
Active
Active
High
Stopped
Hi-Z
Power Down
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC2932PWR | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| TLC2933PW | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| TLC2933PWLE | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| TLC2942PW | HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK |
| TLC32040C | ANALOG INTERFACE CIRCUITS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC2933AIPW | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2933AIPWG4 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2933AIPWR | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2933AIPWRG4 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2933IPW | 功能描述:鎖相環(huán) - PLL Phase Locked Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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