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參數(shù)資料
| 型號： | TLC2543QEP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 中文描述： | 12位模擬數(shù)字轉(zhuǎn)換串行控制和11個模擬輸入 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 364K |
| 代理商： | TLC2543QEP |
www.ti.com
Operating Characteristics
over recommended operating free-air temperature range, V
CC
= V
ref+
= 4.5 V to 5.5 V, f
(I/O CLOCK)
= 4.1 MHz
TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A–JULY 2002–REVISED NOVEMBER 2006
PARAMETER
Linearity error
(2)
Differential linearity error
Offset error
(3)
Gain error
(3)
Total unadjusted error
(5)
TEST CONDITIONS
See
Figure 2
See
Figure 2
See
Figure 2
(4)
See
Figure 2
(4)
MIN
TYP
(1)
MAX
UNIT
LSB
LSB
LSB
LSB
LSB
E
L
E
D
E
O
E
G
E
T
±
1
±
1
±
1.5
±
1
±
1.75
DATA INPUT = 1011
DATA INPUT = 1100
DATA INPUT = 1101
See
Figure 9
through
Figure 14
2048
Self-test output code
(6)
(see
Table 3
)
0
4095
t
(conv)
Conversion time
8
10
μ
s
10 + total
I/O CLOCK
periods +
t
d(I/O-EOC)
Total cycle time
(access, sample, and conversion)
(7)
t
c
See
Figure 9
through
Figure 14
μ
s
I/O
t
acq
Channel acquisition time (sample)
(7)
See
Figure 9
through
Figure 14
4
12
CLOCK
periods
Valid time,
DATA OUT remains valid after I/O
CLOCK
↓
Delay time,
I/O CLOCK
↓
to DATA OUT valid
Delay time,
last I/O CLOCK
↓
to EOC
↓
Delay time,
EOC
↑
to DATA OUT (MSB/LSB)
Enable time,
CS
↓
to DATA OUT (MSB/LSB driven)
Disable time,
CS
↑
to DATA OUT (high impedance)
Rise time, EOC
Fall time, EOC
Rise time, data bus
Fall time, data bus
Delay time, last I/O CLOCK
↓
to CS
↓
to
abort conversion
(8)
t
v
See
Figure 6
10
ns
t
d(I/O-DATA)
See
Figure 6
150
ns
t
d(I/O-EOC)
See
Figure 7
1.5
2.2
μ
s
t
d(EOC-DATA)
See
Figure 8
100
ns
t
PZH
, t
PZL
See
Figure 3
0.7
1.3
μ
s
t
PHZ
, t
PLZ
See
Figure 3
70
150
ns
t
r(EOC)
t
f(EOC)
t
r(bus)
t
f(bus)
See
Figure 8
See
Figure 7
See
Figure 6
See
Figure 6
15
15
15
15
50
50
50
50
ns
ns
ns
ns
t
d(I/O-CS)
5
μ
s
(1)
(2)
(3)
All typical values are at T
= 25
°
C.
Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied
to REF– convert as all zeros (000000000000).
Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
Both the input address and the output codes are expressed in positive logic.
I/O CLOCK period = 1 /(I/O CLOCK frequency) (see
Figure 7
)
Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at
≤
5
μ
s of the
tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5
μ
s and 10
μ
s, the result is uncertain as to whether the
conversion is aborted or the conversion results are valid.
(4)
(5)
(6)
(7)
(8)
6
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