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| 型號： | TLC2543QEP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 中文描述： | 12位模擬數(shù)字轉(zhuǎn)換串行控制和11個模擬輸入 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大小： | 364K |
| 代理商： | TLC2543QEP |
www.ti.com
PRINCIPLES OF OPERATION
Converter Operation
The operation of the converter is organized as a succession of two distinct cycles: the I/O cycle and the actual
conversion cycle.
I/O Cycle
Conversion Cycle
TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A–JULY 2002–REVISED NOVEMBER 2006
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT
and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7–D4), a 2-bit data length
select (D3–D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are
applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the
input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long, depending on
the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last
falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending
on the selected output data length.
During the I/O cycle, the following two operations take place simultaneously:
An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is
shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first
eight clocks during 12- or 16-clock I/O transfers.
The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low,
the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first
output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and
after the first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O
CLOCK.
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to I/O
CLOCK. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O
cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.
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