參數(shù)資料
型號(hào): TLC1225MJ
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28
封裝: CERAMIC, DIP-28
文件頁數(shù): 9/15頁
文件大小: 230K
代理商: TLC1225MJ
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
calibration of comparator offset
The following actions are performed to calibrate the comparator offset:
1.
The IN+ and IN – inputs are internally shorted together so that the converter input is zero. A coarse
comparator offset calibration is performed by storing the offset voltages of the interconnecting
comparator stages on the coupling capacitors that connect these stages (see Figure 1). The storage of
offset voltages is accomplished by closing all switches and then opening switches A and A’, then
switches B and B’, and then C and C’. This process continues until all interconnecting stages of the
comparator are calibrated. After this action, some of the comparator offset remains uncalibrated.
C’
C
GND
B’
A’
B
GND
A
GND
Figure 1. Comparator Offset Null
2.
An A/D conversion is done on the remaining offset with the 8-bit calibration digital-to-analog converters
(DACs) and 8-bit successive-approximation register (SAR), and the result is stored in the RAM.
calibration of the ADC capacitive capacitor array
The following actions are performed to calibrate capacitors in the 13-bit DACs that comprise the ADC’s
capacitive array:
1.
IN + and IN – are internally disconnected from the 13-bit DACs.
2.
The most significant bit (MSB) capacitor is tied to REF, while the rest of the array capacitors are tied to
GND. The A/D conversion result for the remaining comparator offset, obtained in step 2 above, is
retrieved from the RAM and is input to the 8-bit DACs.
3.
Step 1 of the calibration of comparator offset sequence is performed. The 8-bit DAC input is returned to
zero, and the remaining comparator offset is then subtracted; thus, the comparator offset is completely
corrected.
4.
The MSB capacitor is tied to GND, while the rest of the array capacitors (Cx), are tied to REF. An MSB
capacitor voltage error (see Figure 2) on the comparator output occurs if the MSB capacitor does not
equal the sum of the other capacitors in the capacitive array. This error voltage is converted to an 8-bit
word from which a capacitor error is computed and stored in the RAM.
5.
The capacitor voltage error for the next most significant capacitor is calibrated by keeping the MSB
capacitor grounded and then performing the above steps 1 – 4 while using the next most significant
capacitor instead of the MSB capacitor. The seven most significant capacitors are calibrated in this
manner.
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