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參數(shù)資料
| 型號： | TLC1225MJ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 230K |
| 代理商： | TLC1225MJ |
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
aborting a conversion period in process and beginning a new conversion
If a conversion period is initiated while a conversion sequence is in process, the ongoing conversion is aborted
and a new conversion period begins.
reading the conversion result
When both CS and RD go low, all 13 bits of conversion data are output to the I/O bus. The format of the output
is extended sign with 2s-complement, right-justified data. The sign bit D12 is low if VI+ – VI– is positive and high
if VI+ – VI– is negative.
general
reset INT
When reading the conversion data, the falling edge of the first low-going combination of CS and RD reset INT.
The falling edge of the low-going combination of CS and WR also reset INT.
ready out
For high-speed microprocessors, READY OUT allows the TLC1225 to insert a wait state in the microprocessor’s
read or write cycle.
reference voltage (Vref)
This voltage defines the range for | VI+ – VI– |. When | VI+ – VI– | equals Vref, the highest conversion data value
results. When | VI+ – VI– | equals 0, the conversion data value is zero. For a given input, the conversion data
changes ratiometrically with changes in Vref. Calibration should be performed with the same value of Vref that
is used during conversion.
TIE HIGH
TIE HIGH is a digital input and should be tied high.
calibration and conversion period considerations
Calibration of the internal capacitors and A/D conversion are two separate actions. Each action is independently
initiated. A calibration command should be initiated prior to subsequent conversions; it is not necessary to
recalibrate before each conversion. Capacitor calibration is expected to last indefinitely as long as the clock
signal and power are not interrupted. The offset calibration may drift with temperature changes. The
temperature coefficient of the offset point is shown in the electrical characteristics table. Periodic calibration is
recommended. Calibration and conversion commands require 300 and 24 clock cycles, respectively.
The calibrate and conversion commands are initiated by writing control words on the six least significant bits
of the data bus. These control words are written into the IC when either CS or WR goes high. The initiation of
these commands is illustrated in Figure 3. The bit patterns for the commands are shown in Table 1.
Table 1. Conversion Commands
COMMAND
CS +WR
I/O BUS
REQUIRED NUMBER
COMMAND
CS + WR
D15
D14
D13
D12
D11
D10
REQUIRED NUMBER
OF CLOCK CYCLES
Conversion
↑
H
L
X
L
24
Calibrate
↑
L
X
L
300
Calibration is lost when the clock is stopped.
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