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參數(shù)資料
| 型號： | TL7231MD |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FULL LAYER-III ISO/IEC 11172-3 AUDIO DECODER |
| 中文描述： | 完整的Layer -Ⅲ的ISO / IEC 11172-3音頻譯碼器 |
| 文件頁數(shù)： | 9/37頁 |
| 文件大?。?/td> | 468K |
| 代理商： | TL7231MD |
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TL7231MD
SAMSUNG Electronics CO.
9/37
When microcontroller tries to send data to TL7231MD, it should check whether REQSTRM is
active or not. If the signal is active, microcontroller sets its serial interface to transmit mode and
send serial clock and serial data. After transmitting each byte, microcontroller should check
REQSTRM to decide whether next byte is to be transmitted or not.
When microcontroller tries to receive data from TL7231MD, it should check whether REQSTRM
is active or not. If the signal is active, microcontroller sets its serial interface to receive mode
and send serial clock and receive serial data from TL7231MD. After receiving each byte,
microcontroller should check REQSTRM to decide whether TL7231MD will transmit next byte or
not.
HOST INTERFACE PORT (HIP)
Host interface port is used to send commands to and receive status information from
TL7231MD. HIP of TL7231MD is a parallel I/O port that makes a connection to a host processor
easily. Through the HIP, TL7231MD can be used as a memory-mapped peripheral to a host
processor. The HIP can be thought of as an area of dual-port memory that allows
communication between the computational core of the TL7231MD and host. The HIP is
completely asynchronous. The host processor can write data into the HIP while the TL7231MD
is operating at full speed. HIP transfers are managed using interrupt scheme.
HIP contains 21 registers. Four of them are data-in registers (HDI0/HDI1/HDI2/HDI3) and one of
them is a status register (HSR4). The remaining 16 registers are data-out registers
(HDO0/ …HDO15). Data written into HDIs by host are read by TL7231MD. Through these
registers host can give necessary commands to TL7231MD. A command is written into a HDI0,
and the required parameters of the command are written into the HDI1/HDI2/HDI3. The status
register (HSR4) keeps the information whether data written into the data-in registers are read by
TL7231MD. The status register is managed automatically by TL7231MD and can be read by
host. TL7231MD starts HIP command processing when HDI0 register is written. So if any
command requires parameters, user should write parameters first, and then write command.
Serial ID number can be used to check whether given command has been accepted or not.
TL7231MD can receive the serial ID value through HDO0 when TL7231MD has accepted the
given command. Thus when commands are given to TL7231MD with different serial ID numbers,
it can be examined which command is being processed. Serial ID number itself hasn’t any
special meaning. If this feature is not needed, it is not required to send ID values with
commands. Then the value of HDO0 is undetermined. There is an exception for the ID number
convention. If you use HIP command 0Dh(Revision Code), TL7231MD returns the TL7231MD
revision number, not the ID number.
HDOs are written by TL7231MD and can be read by host. All HIP registers should be memory-
mapped into the memory space of the host processor. The address space of those registers is
shown in Table 4. The usable commands are listed in Table 6. The contents reported by HDOs
are shown from Figure 4 to Figure 16.
Table 4.
Address of Host Interface Port Registers
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