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參數(shù)資料
| 型號： | TL7231MD |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FULL LAYER-III ISO/IEC 11172-3 AUDIO DECODER |
| 中文描述： | 完整的Layer -Ⅲ的ISO / IEC 11172-3音頻譯碼器 |
| 文件頁數(shù)： | 6/37頁 |
| 文件大?。?/td> | 468K |
| 代理商： | TL7231MD |
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TL7231MD
6/37
SAMSUNG Electronics Co.
Table 3.
Pin Descriptions
Signal Name
Type
Description
Internal PLL Interface
CPU Clock In.
16.9344MHz crystal clock input.
CPU Clock Out.
16.9344MHz crystal clock output.
Charge Pump Out.
External capacitor should be connected
between this pin and analog ground.
CPUXI
CPUXO
I
O
FILTER
O
Clock Signal
BCLK
O
Processor Clock Output.
Reset & Power Down Control
Chip Reset.
Reset input to the chip. Internal pull down.
Wake Up.
When high, chip is waked up from SLEEP state. This pin
should be remained active at least 1 clock cycle and inactive before
the host issues next SLEEP command. Internal pull down.
Power Down.
This pin controls PWRDOWN state. When high, chip
goes to very low power consumption state. After deactivation,
WAKEUP pin should be remained low at least 150
μ
s. Internal pull
down.
(Restriction: This pin should be active ONLY in SLEEP state.
Otherwise, Chip reset should be activated.)
RESET
I
WAKEUP
I
PWRDN
I
MCU Serial Interface
Serial Clock.
MCU serial interface clock
.
Serial Data.
When MCU transmits data, this data pin is sampled at
negative edge of CLKXRM. When MCU receives data, Data is valid
from negative edge of CLKXRM to next negative edge of CLKXRM.
DXRM should be sampled at positive edge of CLKXRM. After reset,
TL7231MD is set to transmit the most significant bit first.
Request Bit Stream Data.
MCU must check this pin to determine to
continue receiving or transmitting. MCU
should transmit or receive
data during this signal active.
CLKXRM
I
DXRM
I/O
REQSTRM
O
MCU HIP(Host Interface Port) Interface
HIP Enable.
When Low, HIP is selected.
HIP Address Latch Enable.
When High, HD[7:0] should have HIP
address, which is sampled at negative edge of this signal.
HIP Read Enable.
When low, data is loaded to HD[7:0], which
should be sampled at positive edge of this signal.
HIP Write Enable.
Data at HD[7:0] is sampled at positive edge of
this signal.
HIP Address/Data Bus.
Multiplexed address lines and data lines.
HSEL#
I
HALE
I
HRD#
I
HWR#
I
HD[7:0]
I/O
Internal ADC Interface
ADC Analog Input.
Analog input spans between ADCREFP and
ADCREFN.
ADC Internal Reference Top Bias
. Connect this pin to voltage
between ADCVDDA and 2.0V.
ADC Internal Reference Bottom Bias.
Connect this pin to ground.
ADCAIN
I
ADCREFP
I
ADCREFN
I
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