參數(shù)資料
型號(hào)： TL7231MD
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： FULL LAYER-III ISO/IEC 11172-3 AUDIO DECODER
中文描述： 完整的Layer -Ⅲ的ISO / IEC 11172-3音頻譯碼器
文件頁(yè)數(shù)： 30/37頁(yè)
文件大?。?/td> 468K
代理商： TL7231MD
TL7231MD
30/37
SAMSUNG Electronics Co.
Lower Power Operation
TL7231MD has low-power feature that makes the processor get into very low-power dormant
states through hardware or software control. The power saving scheme is explained with the
state diagram of TL7231MD shown in Figure 20.
RUN
In this state, TL7231MD decodes MP3 or compressed voice bit stream, or encodes voice signal.
Also in this state it can process other HIP commands such as 20h and 21h. HIP command 01h,
04h through 09h, and 0Fh should not be used in this state. TL7231MD consumes normal power
at this state, It processes all internal functions and drives external pads. It can transit to WAIT
state with HIP command 00h. When there is no job left or it waits available data, power
consumption is reduced as that of WAIT state.
WAIT
When RESET signal becomes active, TL7231MD goes into WAIT state. There it can transit to
RUN, or SLEEP state. When TL7231MD is in this state, it is ready to receive any HIP
commands from host. It can go into RUN state when it receives HIP commands such as 01h,
04h though 09h. Also it can process other HIP commands such as volume control (21h) etc. in
this state. TL7231MD goes into this state through HIP command 00h from RUN state. When
TL7231MD is in this state, only peripheral interface block consumes power. That is, internally
generated peripheral clock is active but clock for the DSP core logic is not. When it receives HIP
command 0Fh, it goes into SLEEP state in which more power is saved.
SLEEP
In SLEEP state, only internal analog blocks such as PLL, ADC and DAC of TL7231MD
consume power. In this state, internal ADC and DAC are disabled. But PLL consumes normal
operation power. In this state, TL7231MD can transit to PWRDOWN state when external
PWRDN pin becomes active. Active WAKEUP signal changes its state from SLEEP to WAIT.
PWRDOWN
When TL7231MD is in SLEEP state and PWRDN signal becomes active, it transits to
PWRDOWN. To make TL7231MD stay in this state, the external PWRDN signal keep its active
state. When the PWRDN signal becomes inactive, TL7231MD exits from this PWRDOWN state,
and then goes into SLEEP state. When it changes its state from PWRDOWN to SLEEP, this
state should not be changed during minimum 150
μ
s until internal PLL is stabilized. TL7231MD
consumes the minimum power at this state because all internal logic blocks and analog blocks
are power-downed.
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