THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
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SLES032—6/18/02 3:33 PM
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Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
The figure illustrates a shifted analog ramping output. The multiplication factor could be calculated to scale this
output range to the full 10-bit range of the DAC. Note that this scaling can be programmed individually per channel
using registers csm_mult_<gy,rcr,bcb>. The range of the multiplication is 0..1.999, coded as a binary weighted 11-
bit value, thus: csm_mult_<gy,rcr,bcb> = (Desired scale ( 0 to 1.999) / 1.999)
X 2047
Note that this approach allows to scale input code ranges that are different on each channel to an identical full-
scale DAC output compliance, as is required for ITU-R601 sampled signals where Y video data is represented in
the range [64..940] and both Cb,Cr color difference channels are coded within the range [64..960]. All three
channels need to generate a 700mV nominal analog output compliance. Using a combination of FSADJ - adjusting
the full-scale current of all DAC channels simultaneously in the analog domain -, and digital CSM control, different
trade-offs can be made for DAC output amplitude control incl. channel matching.
As will be discussed in the section on the DTG, the user also controls the DAC output levels during blanking,
negative & positive sync, pre-,post-equalization and serration pulses. Using a combination of CSM and DTG
programming, it is therefore possible to accommodate many video standards, incl. those that require a video blank-
to-black level setup, as well as differing video/sync ratios (e.g. 10:4 or 7:3).
Finally using the selectable full-scale adjustment from FSADJ1 or FSADJ2 terminals, it is possible to switch
between two analog output compliance settings with no hardware changes.
Physically the CSM output is represented internally as an 11-bit value to improve the DAC linearity at the 10-bit
level after scaling. Each DAC internally is of 11-bit resolution.