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參數(shù)資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 10/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
18
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
10-bit YCbCr 4:2:2 (ITU mode)
CLKIN is equal to 2x pixel clock since all components are multiplexed on a single 10 bit bus with a 4-multiple
sequence: CbYCrY. Therefore the pixel clock (i.e. the Y input rate) is of CLKIN and the Cb and Cr rate each is
of CLKIN.
When dedicated timing is used in this mode, there is a fixed relationship between the 1
st active period of HS_IN (i.e.
the first CLKIN rising edge seeing HS active) and a Cb color component assumed present during that clock period
on the input bus. When embedded timing is used in this mode, the SAV/EAV structure also unambiguously defines
the CbCr sequence, acc. to ITU-R.BT656 (for 625I & 525I) and to SMPTE293M (for 525P).
16-bit RGB 4:4:4
CLKIN is equal to 1x pixel clock. This format is only supported in VESA mode and can be used for PC graphics
applications that do not require full 8-bit resolution on each color component.
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