參數(shù)資料
型號(hào): THS5641ADW
廠商: Texas Instruments, Inc.
英文描述: 8-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER
中文描述: 8位,100 MSPS的,CommsDACE數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 4/28頁(yè)
文件大?。?/td> 703K
代理商: THS5641ADW
THS5641A
8-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS277 –MARCH 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AV
DD
= 5 V,
DV
DD
= 5 V, IOUT
FS
= 20 mA (unless otherwise noted)
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bits
Resolution
DC accuracy
INL
DNL
Monotonicity
Analog output
8
Integral nonlinearity
Differential nonlinearity
TA= 40
TA = –40
°
C to 85
°
C
–0.25
–0.25
±
0.1
±
0.05
0.25
0.25
LSB
LSB
Monotonic
Offset error
0.02
2.3
1.3
%FSR
Gain error
Without internal reference
With internal reference
%FSR
Full scale output current
2
20
mA
V
V
k
pF
Output compliance range
AVDD = 5 V, IOUTFS = 20 mA
AVDD = 3.3 V IOUTFS = 20 mA
–1
–1
1.25
0.6
Output resistance
Output capacitance
300
5
Reference output
Reference voltage
Reference output current§
Reference input
VEXTIO
Input voltage range
Input resistance
Small signal bandwidth
Input capacitance
Temperature coefficients
Offset drift
1.18
1.22
100
1.32
V
nA
0.1
1.25
V
1
M
MHz
pF
Without CCOMP1
1.3
100
0
Gain drift
Without internal reference
With internal reference
±
40
±
120
±
35
ppm of
FSR/
°
C
Reference voltage drift
Power supply
AVDD
Analog supply voltage
DVDD
Digital supply voltage
Analog supply current
Sleep mode supply current
IDVDD
3
3
5.5
5.5
30
V
V
IAVDD
25
3
5
mA
mA
mA
Sleep mode
5
6
Digital supply current#
Power dissipation
||
AVDD = 5 V, DVDD = 5 V
AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA
IOUTFS = 20 mA
175
100
±
0.4
mW
AVDD
DVDD
Power supply rejection ratio
%FSR/V
±
0.025
Operating range
–40
85
°
C
Measured at IOUT1 in virtual ground configuration.
Nominal full-scale current IOUTFS equals 32X the IBIAS current.
§Use an external buffer amplifier with high impedance input to drive any external load.
Reference bandwidth is a function of external cap at COMP1 pin and signal level.
#Measured at fCLK = 50 MSPS and fOUT= 1 MHz.
||Measured for 50
RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz.
Specifications subject to change
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