參數(shù)資料
型號(hào)： THS5641ADW
廠商： Texas Instruments, Inc.
英文描述： 8-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 8位，100 MSPS的，CommsDACE數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 703K
代理商： THS5641ADW
THS5641A
8-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS277 –MARCH 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
analog current outputs
Figure 26 shows a simplified schematic of the current source array output with corresponding switches.
Differential PMOS switches direct the current of each individual PMOS current source to either the positive
output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined
by the stack of the current sources and differential switches, and is typically >300 k
in parallel with an output
capacitance of 5 pF.
Output nodes IOUT1 and IOUT2 have a negative compliance voltage of –1 V, determined by the CMOS process.
Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5641A device. The
positive output compliance depends on the full-scale output current IOUT
FS
and positive supply voltage AV
DD
.
The positive output compliance equals 1.25 V for AV
DD
= 5 V and IOUT
FS
= 20 mA. For AV
DD
= 3.3 V the output
compliance is limited to 0.6 V. Exceeding the positive compliance voltage adversely affects distortion
performance and integral nonlinearity. The optimum distortion performance for a single-ended or differential
output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V (e.g. when
applying a 50
doubly terminated load for 20 mA full-scale output current). Applications requiring the
THS5641A output (i.e., OUT1 and/or OUT2) to extend its output compliance should size R
LOAD
accordingly.
AVDD
Current Source Array
IOUT1
IOUT2
RLOAD
RLOAD
Current
Sources
Switches
Figure 26. Equivalent Analog Current Output
Figure 27(a) shows the typical differential output configuration with two matched externally resistor loads. The
nominal resistor load of 50
will give a differential output swing of 2 V
PP
when applying a 20 mA full-scale output
current. The output impedance of the THS5641A depends slightly on the output voltage at nodes IOUT1 and
IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 27(b) should be chosen.
In this I–V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The
complementary output should be connected to ground to provide a dc current path for the current sources
switched to IOUT2. Note that the INL/DNL specifications for the THS5641A are measured with IOUT1
maintained at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current
determine the value of the feedback resistor R
FB
. Capacitor C
FB
filters the steep edges of the THS5641A current
output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp
should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be
selected if a single-ended unipolar output is desirable.
相關(guān)PDF資料
PDF描述
THS5641APW 8-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER
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THS5641AIPW 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 100 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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