參數(shù)資料
型號: THS3092DR
廠商: Texas Instruments, Inc.
英文描述: HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS
中文描述: 高壓,低失真,電流反饋運算放大器
文件頁數(shù): 22/34頁
文件大?。?/td> 1605K
代理商: THS3092DR
www.ti.com
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
PowerPAD DESIGN CONSIDERATIONS
The
THS3092/6
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
0.140
0.060
0.060
0.010
vias
Top View
0.035
0.080
0.050
0.176
0.030
0.026
0.010
0.035
0.100
0.300
Pin 1
THS3092
THS3096
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an R
S
since the THS3092/6 are nominally com-
pensated to operate with a 2-pF parasitic load.
Higher parasitic capacitive loads without an RS
are
allowed
as
the
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrin-
sic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-
environment is not necessary onboard, and
in fact, a higher impedance environment im-
proves distortion as shown in the distortion ver-
sus load plots. With a characteristic board trace
impedance based on board material and trace
dimensions, a matching series resistor into the
trace from the output of the THS3092/6 is used
as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective im-
pedance should be set to match the trace im-
pedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case. This does not preserve signal integrity
as well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation due to the voltage
divider formed by the series output into the
terminating impedance.
Socketing a high speed part like the THS3092/6
are not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost im-
possible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS3092/6 parts directly onto the board.
leadframe upon which the die is mounted [see
Figure 66(a) and Figure 66(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see Fig-
ure 66(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal per-
formance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS3092/6 have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing oper-
ation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
signal
gain
increases
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface
mount
with
the,
mechanical methods of heatsinking.
heretofore,
awkward
Figure 66. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
are
available
in
a
Figure 67. DDA PowerPAD PCB Etch and Via
Pattern
22
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