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參數(shù)資料
| 型號(hào)： | THS1408PFB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA |
| 中文描述： | 14位，1/3/8 MSPS的數(shù)字信號(hào)處理器兼容模擬到數(shù)字的，具有內(nèi)部參考和PGA變換器 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 312K |
| 代理商： | THS1408PFB |
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
appear on the digital output 9.5 clock cycles after the input signal was sampled.
S9
S10
S11
S12
CLK
Data
Out
Analog
Input
C1
C2
C3
tw(CLK)
tw(CLK)
td
Figure 1. Sample Timing
The parallel interface of the THS1401/3/8 ADC features 3-state buffers making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register,
and the control register. Which register is read is determined by the address inputs A[1,0]. The ADC results are
available at address 0.
The timing of the control signals is described in the following sections.
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