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參數(shù)資料
| 型號： | THS1408PFB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA |
| 中文描述： | 14位，1/3/8 MSPS的數(shù)字信號處理器兼容模擬到數(shù)字的，具有內(nèi)部參考和PGA變換器 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 312K |
| 代理商： | THS1408PFB |
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal/external reference operation
The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an external
precision reference in case very high dc accuracy is needed.
The REF+ and REF+ outputs are given by:
REF
VBG 1
2
3
and REF–
VBG 1–2
3
If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF– = 0.5 V and
REF =
2 V.
The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band
gap reference is then disconnected and can be substituted by a voltage on the VBG pin.
programmable gain amplifier
The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing
to the PGA gain register (address 1). The range is 0 to 7dB in steps of one dB.
out of range indication
The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs
exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data
outputs and therefore subject to the same pipeline delay.
offset compensation
With the offset register it is possible to automatically compensate system offset errors, including errors caused
by additional signal conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register),
the value in the offset register (address 2) is automatically subtracted from the output of the ADC.
In order to set the correct value of the offset compensation register, the ADC result when the input signal is 0
must be read by the host processor and written to the offset register (address 2).
test modes
The ADC core operation can be tested by selecting one of the available test modes (see control register
description). The test modes apply various voltages to the differential input depending on the setting in the
control register.
digital I/O
The digital inputs and outputs of the THS1401/3/8 ADC are 3-V CMOS compatible. In order to avoid current
feed back errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series
resistors (100
) on the digital outputs can improve the performance by limiting the current during output
transitions.
The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE input low.
Refer to the read and write timing diagrams in the parameter measurement information section for information
on read and write access.
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