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參數(shù)資料
| 型號(hào)： | THS1408PFB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA |
| 中文描述： | 14位，1/3/8 MSPS的數(shù)字信號(hào)處理器兼容模擬到數(shù)字的，具有內(nèi)部參考和PGA變換器 |
| 文件頁(yè)數(shù)： | 15/22頁(yè) |
| 文件大?。?/td> | 312K |
| 代理商： | THS1408PFB |
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THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 4. Control Register, Address 3, Read
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
PWD
REF
FOR
TM2
TM1
TM0
OFF
RES
RES
RES
RES
RES
RES
RES
Table 5. Control Register, Address 3, Write
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
PWD
REF
FOR
TM2
TM1
TM0
OFF
RES
RES
RES
RES
RES
RES
RES
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWD:
REF:
FOR:
TM2–0:
Power down
Reference select
Output format
Test mode
0 = normal operation
0 = internal reference
0 = straight binary
000 = normal operation
001 = both inputs = REF–
010 = IN+ at V
ref
/2, IN– at REF–
011 = IN+ at REF+, IN– at REF–
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF–, IN– at V
ref
/2
111 = IN+ at REF–, IN– at REF+
0 = enable
Must be set to 0.
1 = power down
1 = external reference
1 = 2s complement
OF:
RES
Offset correction
Reserved
1 = disable
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