參數(shù)資料
型號(hào): THS12082DA
廠商: Texas Instruments, Inc.
英文描述: 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
中文描述: 12位,8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 20/38頁(yè)
文件大?。?/td> 517K
代理商: THS12082DA
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271 – MAY 2000
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO trigger level
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13).
If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of
the signal DATA_AV to indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which
can be selected, is dependent on the number of input channels. Either a differential or a single-ended input is
considered as one channel. The processor, therefore, always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
0
0
01
02
0
1
04
04
1
0
08
8
1
1
14
12
timing and signal description of the THS12082
The reading from the THS12082 and writing to the THS12082 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS12082 takes place by an internal RD
int
signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 10). This signal is then used to strobe the
words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to
become valid will make RD
int
active while the write input (WR) is inactive. The first of those external signals going
to its inactive state will then deactivate RD
int
again.
Writing to the THS12082 takes place by an internal WR
int
signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR
. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal
(either CS0, CS1 or WR) to become valid will make WR
int
active while the read input (RD) is inactive. The first
of those external signals going to its inactive state will then deactivate WR
int
again.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 10. Logical Combination of CS0, CS1, RD, and WR
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