參數(shù)資料
型號： THS1031TSSOP
廠商： Texas Instruments, Inc.
英文描述： 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述： 2.7伏。 5.5五，10位，30 MSPS的CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 6/26頁
文件大?。?/td> 358K
代理商： THS1031TSSOP
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, AV
DD
= 3 V, DV
DD
= 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AV
DD
, 2 V
input span from 0.5 V to 2.5 V, external reference, PGA = 1X, T
A
= –40
°
C to 85
°
C (unless otherwise
noted) (continued)
dynamic performance (ADC and PGA)
PARAMETER
TEST CONDITIONS
f = 3.5 MHz
MIN
8.2
TYP
MAX
UNIT
9
ENOB
Effective number of bits
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
8.8
Bits
7.7
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
7.64
55
60
SFDR
Spurious free dynamic range
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
63
dB
48
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
52.4
–58.2
–54.7
THD
Total harmonic distortion
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
–68.7
dB
–47
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
–51.9
51.2
56
SNR
Signal to noise
Signal-to-noise
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
55
dB
53
f = 15 MHz, AVDD = 5 V
f = 3.5 MHz
49.3
51.1
56
SINAD
Signal to noise and distortion
Signal-to-noise and distortion
f = 3.5 MHz, AVDD = 5 V
f = 15 MHz
55
dB
48.1
f = 15 MHz, AVDD = 5 V
47.7
PGA
PARAMETER
MIN
TYP
MAX
UNIT
Gain range (linear scale)
0.5
4
V/V
Gain step size (linear scale)
0.5
Gain error from nominal
3%
Number of control bits
3
Bits
clamp DAC
PARAMETER
MIN
TYP
MAX
UNIT
Resolution
10
Bits
DAC output range
REFBF
REFTF
Clamping analog output voltage range
0.1
AVDD–0.1
+ 40
V
Clamping analog output voltage error
– 40
mV
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