參數(shù)資料
型號: THS1031TSSOP
廠商: Texas Instruments, Inc.
英文描述: 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述: 2.7伏。 5.5五,10位,30 MSPS的CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 23/26頁
文件大?。?/td> 358K
代理商: THS1031TSSOP
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
clamp operation (continued)
requirements
For a single direct source of NTSC video,
The initial clamp acquisition time needs to be between 130
μ
s and 160
μ
s to set the input dc level within
1 mV accuracy.
The clamp pulse at CLAMP is recommended to be 2
μ
s (typ).
The droop voltage needs to be compensated within one clamping period of 64
μ
s for 1 V and 2 V. Input
ranges are 1 mV and 1.9 mV respectively which are less than 1 LSB.
power management
Upon power up, the THS1031 is put in the default mode. In the default mode, the PGA (PGA bypass) and the
clamp DAC are powered down which adds to the device’s flexibility. The users need not incur the penalty of
having to provide power for a certain section if it is not necessary to their design.
When bit 3 of PGA/control register is set to 1, the entire device is powered down. The ADC will wake-up in 400 ns
(typ) after the bit 3 is reset.
相關(guān)PDF資料
PDF描述
THS1031SOIC 2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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THS1050C 10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
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