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參數(shù)資料
| 型號： | THS10064EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | THS10064 Evaluation Module(THS10064評估模塊) |
| 中文描述： | THS10064評估模塊（THS10064評估模塊） |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 662K |
| 代理商： | THS10064EVM |
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EVM Setup
1-4
J3
: selection of the analog input configuration:
J3 inserted between 1 and 4:
selection of the differential input ADIFF (in
combination with J4 set between 1 and 4)
J3 inserted between 2 and 5:
selection of the single ended input AINP
J3 inserted between 3 and 6:
required for the THS12082 and THS10082,
where pin 31 (input AINP of the THS1206) functions as an internal FIFO
overflow indicator (OV_FL). This pin can be monitored during data
converter software debugging.
J4
: selection of the analog input configuration:
J4 inserted between 1 and 4
: selection of the differential input ADIFF (in
combination with J3 set between 1 and 4)
J4 inserted between 2 and 5:
selection of the single ended input AINM
J4 inserted between 3 and 6:
required for the THS12082 and THS10082,
where the input AINM of the THS1206 functions as RESET input. Pin 3 of
J4 is connected to the RESET signal of the common-connector interface.
J5
: selection of the analog input configuration;
J5 inserted between 1 and 2:
selection of the single ended input BINP
J5 inserted between 2 and 3:
selection of the differential input BDIFF (in
combination with J6 set between 2 and 3)
J6
: selection of the analog input configuration:
J6 inserted between 1 and 2:
selection of the single ended input BINM
J6 inserted between 2 and 3:
selection of the differential input BDIFF (in
combination with J5 set between 2 and 3)
J7
: selection of the clock source:
J7 inserted between 1 and 2:
the clock input of the data converter is
connected to the common connector interface. In this case, the DSP
should generate the clock signal.
J7 inserted between 2 and 3:
the clock signal should be applied to the
BNC connector EXT_CLK in this configuration.
J8
: J8 is a connector block where the following digital signals can be
monitored:
Pin
Description
Pin
Description
Pin 1
GND
Pin 6
WR/
Pin 2
CLK
Pin 7
GND
Pin 3
GND
Pin 8
OV_FL
Pin 4
DATA_AV
Pin 9
GND
Pin 5
GND
Pin 10
RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS10064IDA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064IDAG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10B 6 MSPS ADC Quad Ch. DSP/uP Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1007 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1007CDA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1007CDAG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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