參數(shù)資料
型號(hào)： THS10064EVM
廠商： Texas Instruments, Inc.
英文描述： THS10064 Evaluation Module(THS10064評(píng)估模塊)
中文描述： THS10064評(píng)估模塊（THS10064評(píng)估模塊）
文件頁(yè)數(shù)： 8/28頁(yè)
文件大?。?/td> 662K
代理商： THS10064EVM
EVM Setup
1-3
EVM Description
Differential analog input
The THS1206/THS10064 (THS12082/THS10082) provide up to two
(one) differential analog input channels to the analog-to-digital converter.
These two (one) differential inputs are provided on the EVM via the two
BNC connectors, which are labeled ADIFF and BDIFF. The BNC
connector ADIFF does not have any function with the THS12082 and
THS10082, which only feature one differential analog input channel. The
analog input voltage range is from
–
2 V to 2 V. To use the differential mode,
a single ended signal is applied to ADIFF or BDIFF. This signal is
converted into a differential signal by a transformer, and is therefore
ac-coupled. The center tap of the transformer is connected to the common
mode output voltage REFOUT of the analog-to-digital converter. As a
result, the input signal is shifted to the common-mode voltage REFOUT.
Clock circuit
An external clock with frequency up to 6 MHz (8 MHz for the THS10082
and THS12082) is required for operation of the analog-to-digital converter
in the continuous-conversion mode. The external clock source is required
to drive the 50-
BNC input EXT-CLK. The clock signal can also be
generated from the connected processor. J7 should be set to the
appropriate position.
Digital output
The digital output of the analog-to-digital converter is applied to connector
block J9 and is also connected to the data bus of the
common connector
interface. No latch is used between the analog-to-digital converter and J9.
The analog-to-digital converter is able to drive up to 30 pF at the data bus
D0
–
D11 (D0
–
D9 for the THS10064 and THS10082).
1.4
EVM Setup
The EVM provides a platform for lab-prototype evaluation. Typically, it is
operated by using a Texas Instruments DSP kit or evaluation module.
J1:
selection of the analog supply voltage:
J1 inserted between 1 and 2:
the supply voltage (5 V) is taken from the
DSP starter kit or evaluation module with the
common-connector
inter-
face. No external analog supply voltage is required in this configuration.
J1 inserted between 2 and 3:
for use of an external dc power supply (6 V
to 10 V). The supply voltage, ranging from 6 V to 10 V, is regulated to 5 V by
using the Texas Instruments low-dropout regulator TPS7250.
J2
: selection of the digital supply voltage:
J2 inserted between 1 and 2:
the supply voltage (3.3 V) is taken from the
DSP starter kit or evaluation module with the
common-connector
interface. No external digital supply voltage is required in this
configuration.
J2 inserted between 2 and 3:
for use of an external dc power supply (6 V
to 10 V). The supply voltage, ranging from 6 V to 10 V, is regulated to 3.3 V
by using the Texas Instruments low-dropout regulator TPS7233.
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