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參數資料
| 型號： | THS10064DA |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10 - MSPS的第6位，同步采樣模擬數字轉換器 |
| 文件頁數： | 22/41頁 |
| 文件大?。?/td> | 543K |
| 代理商： | THS10064DA |
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THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO trigger level
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13).
If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of
the signal DATA_AV to indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which
can be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is
considered as one channel. The processor therefore always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
TRIGGER LEVEL
FOR 3 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 4 CHANNELS
(ADC values)
0
0
01
02
03
04
0
1
04
04
06
08
1
0
08
08
09
12
1
1
14
12
12
Reserved
Timing and Signal Description of the THS10064
The reading from the THS10064 and writing to the THS10064 is perfomed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write ouput signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS10064 takes place by an internal RD
int
signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 12). This signal is then used to strobe the
words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to
become valid will make RD
int
active while the write input (WR) is inactive. The first of those external signals going
to its inactive state will then deactivate RD
int
again.
Writing to the THS10064 takes place by an internal WR
int
signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control
registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WR
int
active while
the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate
WR
int
again.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 12. Logical Combination of CS0, CS1, RD, and WR
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS10064EVM | 制造商:Texas Instruments 功能描述:THS10064 10-BIT, 6 MSPS, DC EVM - Bulk |
| THS10064IDA | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064IDAG4 | 功能描述:模數轉換器 - ADC 10B 6 MSPS ADC Quad Ch. DSP/uP Interface RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1007 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1007CDA | 功能描述:模數轉換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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