參數(shù)資料
型號(hào): THS10064DA
廠商: Texas Instruments, Inc.
英文描述: 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
中文描述: 10 - MSPS的第6位,同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 14/41頁
文件大?。?/td> 543K
代理商: THS10064DA
THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO description
In order to facilitate an efficient connection to today’s processors, the THS10064 is supplied with a FIFO. This
integrated FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as
a flexible circular buffer. The circular buffer integrated in the THS10064 can store up to 16 conversion values.
Therefore, the amount of interrupts to be served by a processor can be reduced significantly.
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
Read Pointer
Trigger Pointer
Write Pointer
Data in FIFO
Free
Figure 6. Circular Buffer
The converted data of the THS10064 is automatically written into the FIFO. To control the writing and reading
process, a write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the
location which will be read next. The write pointer indicates the location which contains the last written sample.
With a selection of multiple analog input channels, the converted values are written in a predefined sequence
to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is
continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a
specific trigger level according to Table 13 in order to choose the configuration which best fits the application.
The FIFO provides the signal DATA_AV, which signals the processor to read the amount of data equal to the
trigger level selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied.
The trigger condition is satisfied when as many values as selected for the trigger level where written into the
FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine
call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents
the first channel according to the autoscan mode, which is shown in Table 10. The channel information is
therefore always maintained.
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