參數(shù)資料
型號(hào)： THS10064DA
廠商： Texas Instruments, Inc.
英文描述： 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
中文描述： 10 - MSPS的第6位，同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 11/41頁(yè)
文件大?。?/td> 543K
代理商： THS10064DA
THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
continuous conversion mode
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.
In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running
external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is
written into the FIFO. The first conversion value is written into the FIFO with a latency of 8 + TL (trigger level)
clock cycles after the FIFO reset.
Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case
of a trigger level set to 1 or 4.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7
Channel 1
Sample N+8
Channel 1
Data N–5
Channel 1
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N+3
Channel 1
td(A)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
td(O)
td(DATA_AV)
td(DATA_AV)
AIN
CONV_CLK
Data Into
FIFO
DATA_AV,
Trigger Level = 1
DATA_AV,
Trigger Level = 4
td(pipe)
50%
50%
Figure 2. Timing of Continuous Conversion Mode (1-channel operation)
Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows
the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger
level set to 2 or 4.
AIN
CONV_CLK
Data Into
FIFO
DATA_AV,
Trigger Level = 2
DATA_AV,
Trigger Level = 4
Data N–3
Channel 2
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N+1
Channel 2
td(DATA_AV)
tw(CONV_CLKH)
tw(CONV_CLKL)
50%
td(A)
Sample N
Channel 1,2
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
tc
td(O)
td(Pipe)
td(DATA_AV)
50%
Figure 3. Timing of Continuous Conversion Mode (2-channel operation)
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THS10064IDAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10B 6 MSPS ADC Quad Ch. DSP/uP Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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