參數(shù)資料
型號: TE28F800B3B110
廠商: INTEL CORP
元件分類: DRAM
英文描述: SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述: 512K X 16 FLASH 2.7V PROM, 110 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數(shù): 33/55頁
文件大?。?/td> 638K
代理商: TE28F800B3B110
E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
33
SEE NEW DESIGN RECOMMENDATIONS
TEST POINTS
INPUT
OUTPUT
1.5
3.0
0.0
1.5
NOTE:
AC test inputs are driven at 3.0 V for a logic
“1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
0530_12
Figure 12. 3.3 V Inputs and Measurement Points
TEST POINTS
INPUT
OUTPUT
2.0
0.8
0.8
2.0
2.4
0.45
NOTE:
AC test inputs are driven at V
(2.4 V
) for a logic “1” and V
(0.45 V
) for a logic “0.” Input timing begins at V
IH
(2.0 V
TTL
)
and V
IL
(0.8 V
TTL
) . Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%) <10 ns.
0530_13
Figure 13. 5 V Inputs and Measurement Points
C
L
OUT
V
CC
DEVICE
UNDER
TEST
R
1
R
2
0530_14
NOTE:
See table for component values.
Figure 14. Test Configuration
Test Configuration Component Values
Test Configuration
C
L
(pF)
R
1
(
) R
2
(
)
3.3 V Standard Test
50
990
770
5 V Standard Test
100
580
390
5 V High-Speed Test
30
580
390
NOTE:
C
L
includes jig capacitance.
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