參數(shù)資料
型號(hào)： TE28F640C3
廠商： Intel Corp.
英文描述： 3 Volt Intel Advanced+ Boot Block Flash Memory
中文描述： 3伏英特爾高級(jí)啟動(dòng)塊閃存
文件頁(yè)數(shù)： 28/58頁(yè)
文件大?。?/td> 920K
代理商： TE28F640C3
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
22
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2. Since each column lists specifications for a different V
and V
voltage range combination, the test
conditions V
Max, V
Max, V
Min, and V
Min refer to the maximum or minimum V
CC
or V
CCQ
voltage listed at the top of each column. V
CC
Max is 3.3 V on 0.25
μ
m 32-Mbit devices.
3. Automatic Power Savings (APS) reduces I
CCR
to approximately standby levels in static operation.
4. Sampled, not 100% tested.
5. Erase and program are inhibited when V
< V
and not guaranteed outside the valid V
ranges of
V
, V
V
and V
PP4.
For read operations or during idle time, a 5 V supply may be applied to V
PP
indefinitely. However, V
must be at valid levels for program and erase operations.
6. Applying V
= 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the
main blocks and 2500 cycles on the parameter blocks. V
may be connected to 12 V for a total of 80 hours
maximum. See
Section 3.4
for details. For read operations or during idle time, a 5 V supply may be applied to
V
PP
indefinitely. However, V
PP
must be at valid levels for program and erase operations.
NOTE:
AC test inputs are driven at V
CCQ
for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
timing ends, at V
CCQ
/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
when V
CCQ
= V
CCQ
Min.
0580_06
NOTE:
See table for component values.
NOTE:
C
L
includes jig capacitance.
Figure 5. Input/Output Reference Waveform
TEST POINTS
INPUT
OUTPUT
V
CCQ
0.0
V
CCQ
2
V
CCQ
2
Figure 6. Test Configuration
C
L
Out
V
CCQ
Device
under
Test
R
1
R
2
Test Configuration Component Values for Worst
Case Speed Conditions
Test Configuration
C
L
(pF)
R
1
(
)
R
2
(
)
V
CCQ1
Standard Test
50
25 K
25 K
V
CCQ2
Standard Test
50
14.5 K
14.5 K
V
CCQ3
Standard Test
50
16 K
16 K
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