參數(shù)資料
型號(hào)： TE28F320C3
廠商： Intel Corp.
英文描述： 3 Volt Intel Advanced+ Boot Block Flash Memory
中文描述： 3伏英特爾高級(jí)啟動(dòng)塊閃存
文件頁(yè)數(shù)： 12/58頁(yè)
文件大?。?/td> 920K
代理商： TE28F320C3
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
6
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Table 2. 3 Volt Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally latched during a program or
erase cycle.
28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20],
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
DQ
0
–DQ
7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle during a Program
command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DQ
8
–
DQ
15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle during a Program
command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state
when the chip is de-selected.
Not included on x8 products.
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#
is active low. CE# high de-selects the memory device and reduces power consumption to standby
levels.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers during a read operation.
OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and memory array. WE# is active low.
Addresses and data are latched on the rising edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to control reset/deep power-down
mode.
When RP# is at logic low, the device is in reset/deep power-down mode
, which drives the outputs
to High-Z, resets the Write State Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation
. When RP# transitions from logic-
low to logic-high, the device defaults to the read array mode.
WP#
INPUT
WRITE PROTECT:
Provides a method for locking and unlocking the two lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked
, preventing program and erase
operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and
either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked
and can be programmed or erased.
See
Section 3.3
for details on write protection.
V
CCQ
INPUT
OUTPUT V
CC
:
Enables all outputs to be driven to 1.8 V – 2.5 V while the V
CC
is at 2.7 V–3.3 V. If the
V
CC
is regulated to 2.7 V–2.85 V, V
CCQ
can be driven at 1.65 V–2.5 V to achieve lowest power
operation (see
Section 4.4
)
.
This input may be tied directly to V
CC
(2.7 V–3.6 V).
V
CC
DEVICE POWER SUPPLY:
2.7 V–3.6 V
V
PP
PROGRAM/ERASE POWER SUPPLY:
Supplies power for program and erase operations. V
PP
may
be the same as V
CC
(2.7 V–3.6 V) for single supply voltage operation. For fast programming at
manufacturing, 11.4 V–12.6 V may be supplied to V
PP
. This pin cannot be left floating. Applying
11.4 V–12.6 V to V
PP
can only be done for a maximum of 1000 cycles on the main blocks and 2500
cycles on the parameter blocks.
V
PP
may be connected to 12 V for a total of 80 hours maximum (see
Section 3.4
for details).
V
PP
< V
PPLK
protects memory contents against inadvertent or unintended program and erase
commands.
GND
GROUND:
For all internal circuitry. All ground inputs
must
be connected.
NC
NO CONNECT:
Pin may be driven or left floating.
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TE28F320C3BA70 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3)
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