參數(shù)資料
型號: TE28F320B3BC70
廠商: INTEL CORP
元件分類: DRAM
英文描述: 3 Volt Advanced Boot Block Flash Memory
中文描述: 2M X 16 FLASH 2.7V PROM, 70 ns, PDSO48
封裝: 12 X 20 MM, TSOP-48
文件頁數(shù): 32/58頁
文件大?。?/td> 920K
代理商: TE28F320B3BC70
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
26
3UHOLPLQDU\
AC Characteristics, Continued
NOTES:
1. OE# may be delayed up to t
t
GLQV
after the falling edge of CE# without impact on t
ELQV
.
2. Sampled, but not 100% tested.
See
Figure 7
for the AC waveform for read operations.
See
Figure 5, “Input/Output Reference Waveform” on page 22
for timing measurements and maximum
allowable input slew rate.
#
Sym
Parameter
Density
64 Mbit
Unit
Product
90 ns
100 ns
V
CC
2.7 V
–3.6 V
2.7 V–3.6 V
Note
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
PHQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
Read Cycle Time
Address to Output Delay
CE# to Output Delay
OE# to Output Delay
RP# to Output Delay
CE# to Output in Low Z
OE# to Output in Low Z
CE# to Output in High Z
OE# to Output in High Z
Output Hold from Address, CE#, or
OE# Change, Whichever Occurs First
90
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
90
90
20
150
100
100
20
150
1
1
2
2
2
2
0
0
0
0
20
20
20
20
R10
t
OH
2
0
0
ns
Figure 7. AC Waveform: Read Operations
High Z
Valid Output
Address Stable
Data Valid
Device
Address Selection
Standby
ADDRESSES (A)
V
IH
V
IL
V
IH
V
IL
CE# (E)
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
High Z
V
IH
V
IL
R1
R2
R4
R3
R5
R6
R7
R8
R9
R10
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