參數(shù)資料
型號: TE28F256P30
廠商: Intel Corp.
英文描述: Intel StrataFlash Memory (J3)
中文描述: 英特爾StrataFlash存儲器(J3)
文件頁數(shù): 51/72頁
文件大?。?/td> 905K
代理商: TE28F256P30
256-Mbit J3 (x8/x16)
Datasheet
51
10 = pulse on Program Complete
Used to generate a system interrupt pulse when any flash device in
an array has completed a program operation. Provides highest
performance for servicing continuous buffer write operations.
11 = pulse on Erase or Program
Complete
Used to generate system interrupts to trigger servicing of flash arrays
when either erase or program operations are completed, when a
common interrupt service routine is desired.
NOTES:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both SR.4 and SR.5 being set.
Table 22. STS Configuration Coding Definitions
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Pulse on
Program
Complete
(1)
Pulse on
Erase
Complete
(1)
D[1:0]
= STS Configuration Codes
Notes
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