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參數(shù)資料
| 型號(hào)： | TE28F128P30T85 |
| 廠(chǎng)商： | INTEL CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 85 ns, PDSO56 |
| 封裝： | 14 X 20 MM, TSOP-56 |
| 文件頁(yè)數(shù)： | 46/102頁(yè) |
| 文件大?。?/td> | 1609K |
| 代理商： | TE28F128P30T85 |
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1-Gbit P30 Family
April 2005
46
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then V
CC
should attain V
CCMIN
before
applying V
CCQ
and V
PP
. Device inputs should not be driven before supply voltage equals V
CCMIN
.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
Num Symbol
P1
t
PLPH
Parameter
Min
100
-
-
60
Max
-
25
25
-
Unit
ns
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
CC
Power valid to RST# de-assertion (high)
P2
t
PLRH
μs
P3
t
VCCPH
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
is < t
PLPH
MIN, but this is not guaranteed.
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
If RST# is tied to the V
supply, device will not be ready until t
after V
≥
V
.
If RST# is tied to any supply/signal with V
CCQ
voltage levels, the RST# input voltage must not exceed
V
until V
≥
V
.
Reset completes within t
PLPH
if RST# is asserted while no erase or program operation is executing.
7.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TE28F128P30T85A | 功能描述:IC FLASH 128MBIT 85NS 56TSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ |
| TE28F128P30XXX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| TE28F128P33B85A | 功能描述:IC FLASH 128MBIT 85NS 56TSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ |
| TE28F128P33T85A | 功能描述:IC FLASH 128MBIT 85NS 56TSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線(xiàn)） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| TE28F160B3 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
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