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參數(shù)資料
| 型號： | TE28F128J3C-150 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 8M X 16 FLASH 2.7V PROM, 150 ns, PDSO56 |
| 封裝： | 14 X 20 MM, TSOP-56 |
| 文件頁數(shù)： | 44/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | TE28F128J3C-150 |
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256-Mbit J3 (x8/x16)
44
Datasheet
12.0
Erase Operations
Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once
a block is erased, all bits within that block will read as a logic level one. To determine the status of
a block erase, poll the Status Register and analyze the bits. This following section describes block
erase operations in detail.
12.1
Block Erase
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires an appropriate
address within the block to be erased (erase changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle
block erase sequence is written, the device automatically outputs SRD when read (see
Figure 22,
“Block Erase Flowchart” on page 63
). The CPU can detect block erase completion by analyzing
the output of the STS signal or SR.7. Toggle OE#, CE0, CE1, or CE2 to update the Status Register.
When the block erase is complete, SR.5 should be checked. If a block erase error is detected, the
Status Register should be cleared before system software attempts corrective actions. The CUI
remains in Read Status Register mode until a new command is issued.
This two-step command sequence of setup followed by execution ensures that block contents are
not accidentally erased. An invalid Block Erase command sequence will result in both SR.4 and
SR.5 being set. Also, reliable block erasure can only occur when V
CC
is valid and V
PEN
= V
PENH
.
If block erase is attempted while V
PEN
≤
V
PENLK
, SR.3 and SR.5 will be set. Successful block
erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the
corresponding block lock-bit is set, SR.1 and SR.5 will be set.
12.2
Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or program data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs SRD when read after the Block Erase Suspend command is written.
Polling SR.7 then SR.6 can determine when the block erase operation has been suspended (both
will be set). In default mode, STS will also transition to V
OH
. Specification t
WHRH
defines the
block erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A program command sequence can also be issued during erase suspend to program
data in other blocks. During a program operation with block erase suspended, SR.7 will return to
“0” and STS output (in default mode) will transition to V
OL
. However, SR.6 will remain “1” to
indicate block erase suspend status. Using the Program Suspend command, a program operation
can also be suspended. Resuming a suspended programming operation by issuing the Program
Resume command allows continuing of the suspended programming operation. To resume the
suspended erase, the user must wait for the programming operation to complete before issuing the
Block Erase Resume command.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TE28F128J3C150-MTD | 制造商:Intel 功能描述:ITLTE28F128J3C150-MTD 128MEG STRATA FLAS |
| TE28F128J3C150SL759 | 功能描述:IC FLASH 128MBIT 150NS 56TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
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| TE28F128J3D-75 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx? Embedded Flash Memory (J3 v. D) |
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