參數(shù)資料
型號: TE28F001BX-T150
廠商: INTEL CORP
元件分類: DRAM
英文描述: 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
中文描述: 128K X 8 FLASH 12V PROM, 150 ns, PDSO32
封裝: 8 X 20 MM, 1.20 MM HEIGHT, TSOP-32
文件頁數(shù): 14/33頁
文件大?。?/td> 436K
代理商: TE28F001BX-T150
28F001BX-T/28F001BX-B
290406–9
Bus
Command
Comments
Operation
Write
Erase
Suspend
Data
e
B0H
Write
Erase
Data
e
70H
Status Register
Standby/
Read
Read Status Register
Check SR.7
1
e
Ready, 0
e
Busy
Toggle OE
Y
or CE
Y
to
Update Status Register
Standby
Check SR.6
1
e
Suspended
Write
Read Array
Data
e
FFH
Read
Read array data from
block other than that
being erased.
Write
Erase Resume
Data
e
D0H
Figure 11. 28F001BX Erase Suspend/Resume Flowchart
Programming Equipment
For PROM programming equipment that cannot
bring RP
Y
to high voltage, OE
Y
provides an alter-
nate boot block access mechanism. OE
Y
must tran-
sition to V
HH
a minimum of 480 ns before the initial
program/erase setup command and held at V
HH
at
least 480 ns after program or erase confirm com-
mands are issued to the device. After this interval,
OE
Y
can return to normal TTL levels.
DESIGN CONSIDERATIONS
Three-Line Output Control
Flash memories are often used in larger memory ar-
rays. Intel provides three control inputs to accommo-
date multiple memory connections. Three-line con-
trol provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CE
Y
, while OE
Y
should be
connected to all memory devices and the system’s
READ
Y
control line. This assures that only selected
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode. RP
Y
should be connected to the system POWERGOOD
signal to prevent unintended writes during system
power transitions. POWERGOOD should also toggle
during system reset.
14
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