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參數(shù)資料
| 型號： | TDIS |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC1800 Series of In-System Programmable Configuration PROMs |
| 中文描述： | XC1800系列在系統(tǒng)可編程配置PROM的 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TDIS |
R
September 17, 1999 (Version 1.3)
11
XC1800 Series of In-System Programmable Configuration PROMs
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3 volts. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V V
CC
power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V
CC
), and the output power supply
(V
CCO
) may have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
Reset Activation
On power up, OE/RESET is held low until the XC1800 is
active (1ms) and able to supply data after receiving a CCLK
pulse from the FPGA. OE/RESET is connected to an exter-
nal resistor to pull OE/RESET HIGH releasing the FPGA
INIT and allowing configuration to begin. OE/RESET is
held low until the XC1800 voltage reaches the operating
voltage range. If the power drops below 2.0 Volts, the
PROM will reset.
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input. JTAG
pins TMS, TDI and TDO can be 3-state or high.
Note:
TC = Terminal Count = highest address value. TC+1 = address 0.
Table 6: Truth Table for PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET
CE
DATA
CEO
I
cc
Low
Low
if address < TC: increment
if address > TC: don’t change
Held reset
Held reset
Held reset
active
3-state
3-state
3-state
3-state
High
Low
High
High
High
active
reduced
active
standby
standby
High
Low
High
Low
High
High
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