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參數(shù)資料
| 型號： | TDA9950TT/C2,512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT360-1, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 112K |
| 代理商： | TDA9950TT/C2,512 |
TDA9950_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 November 2007
13 of 24
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
The length of the message is given by the byte in the rst CEC Data Register. This will
be at least 3 for the shortest message. A value less than 3 indicates an invalid
message.
If fewer CEC Data Registers are written than the number indicated by the rst CEC
Data Register, the partial message will be ignored and no conrmation will be
returned.
If more CEC Data Registers are written than the number indicated by the rst CEC
Data Register, the message will be processed as soon as the message's last CEC
Data Register is written, and the extra bytes written will be ignored.
If the highest CEC Data Register is written and more message bytes are indicated by
the rst CEC Data Register, the message will be processed as soon as the highest
CEC Data Register is written, and the extra bytes written will be ignored.
8.6.2 Notes on reading the CEC Data Registers
The CEC Data Registers only contain a valid message when the INT line is set and
the INT bit in the TDA9950 Status Register is set.
If CEC Data Registers are read when the INT line is not set, the rst CEC Data
Register will contain 0, indicating that there are no bytes to read. Any further reads
before a STOP condition will return the value FFh.
The CEC Data Registers should be read starting from the rst CEC Data Register, for
the number of registers indicated by that rst CEC Data Register, in one contiguous
operation.
If the host writes CEC Data Registers and then begins reading without rst resetting
the Address Pointer Register, reading will automatically commence from the rst CEC
Data Register.
If reading stops before all indicated CEC Data Registers are read, the TDA9950 will
reset the INT line and the message is discarded by the TDA9950 and will not be
available for reading again.
If reading continues for more CEC Data Registers than are indicated by the rst CEC
Data Register, the value FFh will be read. The INT line is reset when the last valid
CEC Data Register for the current message is read.
8.7 Using the TDA9950
8.7.1 Initialization
After a reset, rst congure the TDA9950 with its logical address or addresses (as
required):
I2C_WRITE: 04h, 00h, 08h
Set Address Pointer to 04h (ACKH), set ACKH to 00h, and set ACKL to 08h.
The TDA9950 is now congured to acknowledge messages to the logical address 3
(Tuner 1 (see HDMI1.3a specication) or STB1 (see HDMI1.2a specication)).
Then set the TDA9950 to the ON state (mandatory):
I2C_WRITE: 03h, 40h
Set Address Pointer to 03h (CCR), set CCR to 40h.
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