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參數(shù)資料
| 型號(hào)： | TDA9950TT/C2,512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT360-1, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 112K |
| 代理商： | TDA9950TT/C2,512 |
TDA9950_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 November 2007
5 of 24
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
8.
Functional description
The TDA9950 uses an internal processor with embedded software to control the interface
between the CEC line and the I2C-bus.
8.1 Device addressing
The TDA9950 is a slave I2C-bus device and the SCL pin is an input pin only. The timing
and protocol for the I2C-bus are standard.
[1]
The Most Signicant Bit (MSB), b7, is sent rst.
A1 and A0 are hardware-selectable pins.
In case of independent CEC, a system could have up to four TDA9950 devices on the
same I2C-bus.
The four addresses are dened by the state of the inputs A0 and A1 (logic 1 when
connected to VDD, logic 0 when connected to GND).
8.2 Conguring the TDA9950
The TDA9950 is controlled via a series of registers.
The rst byte of any I2C-bus write frame congures the address pointer register APR,
which determines the rst TDA9950 register that will be read or written in the remainder of
the I2C-bus transfer. If a read is carried out without a prior write to the address pointer
register, the register returned will be that to which the address pointer register was last
set.
The address pointer auto-increments after a successful read or write for all address
pointer values other than 00h. Auto-incremented addresses above 19h are invalid and
ignored.
Table 4.
Device address code
Address code
Device code
Chip enable
R/W
Bit
b7[1]
b6
b5
b4
b3
b2
b1
b0
Value
01101A1
A0
R/W
Table 5.
I2C-bus register conguration
Register
Description
Address
Read/Write
APR
Address Pointer Register
00h
W
CSR
TDA9950 Status Register
00h
R
CER
TDA9950 Error Register
01h
R
CVR
TDA9950 Version Register
02h
R
CCR
TDA9950 Control Register
03h
R/W
ACKH
CEC Address ACK High register
04h
R/W
ACKL
CEC Address ACK Low register
05h
R/W
CCONR
CEC Conguration Register
06h
R/W
CDR
CEC Data Registers
07h - 19h
R/W
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