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參數(shù)資料
| 型號： | TDA9950TT/C2,512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT360-1, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 112K |
| 代理商： | TDA9950TT/C2,512 |
TDA9950_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 November 2007
4 of 24
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
7.2 Pin description
[1]
I = input, O = output, P = power supply.
Table 3.
Pin description
Symbol
Pin
Type[1]
Description
CEC_POL
1
I
CEC_POL — Sets the polarity of the signal on pin CEC_OUT.
Leave oating or pull-up to VDD for bit starting with falling edge
(CEC line), or connect to VSS for bit starting with rising edge
(transistor gate). This input is latched at reset.
INT
2
O
INT — Interrupt line to the host processor to indicate data is
available for reading. The polarity of this signal depends on the
state of pin INT_POL.
CEC_OUT
3
O
CEC_OUT — Output for CEC line (open-drain). The polarity of
this signal depends on the state of pin CEC_POL.
RST
4
I
RST — External reset input. A LOW state on this pin resets the
translator.
VSS
5P
Ground: 0 V reference (GND).
XTAL1
6
I
XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (12 MHz crystal).
XTAL2
7
O
XTAL2 — Output from the oscillator amplier.
CEC_IN
8
I
CEC_IN — Input for CEC line.
SDA
9
I/O
SDA — I2C-bus serial data input/output (open-drain).
SCL
10
I
SCL — I2C-bus serial clock input.
RSVD2
11
I
RSVD2 — Reserved pin (should be connected to ground).
RSVD3
12
O
RSVD3 — Reserved pin.
RSVD4
13
O
RSVD4 — Reserved pin.
RSVD5
14
I
RSVD5 — Reserved pin (should be connected to ground).
VDD
15
P
Power supply — This is the (core digital 3.3 V) power supply
voltage for normal operation as well as Idle and Power-down
modes.
RSVD6
16
I
RSVD6 — Reserved pin (should be connected to ground).
RSVD7
17
I
RSVD7 — Reserved pin (should be connected to ground).
INT_POL
18
I
INT_POL — Sets the polarity of the active output required on
the INT signal (pin 2). Leave oating or pull-up to VDD for a
HIGH output when active (rising edge), connect to VSS for a
LOW output when active (falling edge). This input is latched at
reset.
A1
19
I
A1 — I2C-bus slave address bit 2.
A0
20
I
A0 — I2C-bus slave address bit 1.
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