參數(shù)資料
型號(hào)： TDA9910HW/8/C1
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 12-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, PLASTIC, SOT545-2, MS-026, HTQFP-48
文件頁(yè)數(shù)： 21/21頁(yè)
文件大小： 128K
代理商： TDA9910HW/8/C1
TDA9910_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 12 June 2007
9 of 21
NXP Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
[1]
Guaranteed by design.
[2]
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case CLKN pin has to be connected to the ground.
[3]
The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to VCCA.
[4]
Output data acquisition: the output data is available after the maximum delay of td(o).
[5]
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[6]
The total harmonic distortion is obtained with the addition of the rst ve harmonics.
[7]
The signal-to-noise ratio takes into account all harmonics above ve and noise up to Nyquist frequency.
[8]
Intermodulation measured relative to either tone with analog input frequencies fi1 and fi2. The two input signals have the same amplitude
and the total amplitude of both signals provides full-scale to the converter (
6 dB below full-scale for each input signal).
d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; d2(IM2) is
the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
SNR
signal-to-noise ratio[7]
fi = 21.4 MHz
-
67.4
-
dBc
fi = 93 MHz
63
67.2
-
dBc
fi = 175 MHz
-
66.5
-
dBc
SFDR
spurious free dynamic
range
fi = 21.4 MHz
-
76
-
dBc
fi = 93 MHz
68
78
-
dBc
fi = 175 MHz
-
74
-
dBc
ACPR
adjacent channel power
rejection
fi = 93 MHz; 5 MHz
channel spacing;
B = 3.84 MHz
-70
-
dB
d2(IM2)
second order
intermodulation
distortion[8]
fi1 = 21 MHz;
fi2 =22MHz
-
89
-
dBFS
fi1 = 91.5 MHz;
fi2 = 94.5 MHz
-
86
-
dBFS
fi1 = 174 MHz;
fi2 = 176 MHz
-
83
-
dBFS
d3(IM3)
third order
intermodulation
distortion[8]
fi1 = 21 MHz;
fi2 =22MHz
-
88
-
dBFS
fi1 = 91.5 MHz;
fi2 = 93.5 MHz
-
82
-
dBFS
fi1 = 174 MHz;
fi2 = 176 MHz
-
83
-
dBFS
Table 5.
Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 °C
to +85
°C; Vi(IN) Vi(INN) = 0.5 dBFS; VFSIN =VCCA 1.87 V; Vi(CM) =VCCA 1.95 V; typical values measured at
VCCA =VCCD =5V, VCCO = 3.3 V, Tamb =25 °C and CL = 10 pF; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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